Fault tolerance of one-time programmable FPGAs with faulty routing resources

This paper presents a novel approach for fault tolerance of one-time programmable FPGAs by reassignment of routing resouces. As the underlying problem is NP-complete, a greedy algorithm is proposed to provide rapid, but suboptimal solutions. Due to the one-time programmable characteristic of the switches (commonly referred to as antifuses), only unused (fault-free) routing resources must be utilized for reassignment in a chip with a faulty interconnect. We specifically investigate whether reassignment could be accomplished without changing the global routing of any connections. A RC-tree model for the net delay is also presented; delay bounds are established to fully quantify the degradation due to the reassignment. Extensive simulation results are provided.