The power of dynamic reconfiguration

Summary form only given. Advances in semiconductor technology have led to many devices in which the computing devices can be configured as the computation proceeds. Field Programmable Gate Arrays is a typical commercially available configurable device. Such configurability offers several opportunities to speed-up computations. However, algorithmic innovations are needed to exploit such features to obtain fast parallel solutions. This talk will introduce and illustrate algorithmic configurable computing and contrast it with traditional approach based on logic synthesis. This talk will begin with the theoretical foundations of such computations by introducing the Reconfigurable Mesh model that was defined by USC researchers and others several years ago. Dynamic reconfiguration, in which the connections are changed as the computation proceeds is a powerful mechanism to achieve fast parallel solutions. We will illustrate the power of dynamic reconfiguration using this abstract model and show how scalable and portable solutions can be designed using currently available devices which offer limited configurability. These ideas will be illustrated by a number of examples from the USC MAARC project.