Test generation for stuck-at and gate-delay faults in sequential circuits: a mixed functional/structural method

This paper presents a mixed approach for sequential circuit test pattern generation employing the accuracy of structural algorithms and the speed of a pattern generator working at the functional level. The new strategy selects from the State Transition Graph of a Finite State Machine the appropriate edges that allow a functional test pattern generator (FSMTest) to build test sequences covering 100% of the detectable single stuck-at and gate-delay faults. Experiments and comparisons are presented to justify the proposed test strategy.