A CMOS fault tolerant architecture for switch-level faults

This paper presents the application of a new fault tolerant methodology to multiple output CMOS static gates. The adopted fault models include line stuck-at, transistor stuck-open, transistor stuck-on and bridging faults, thus covering a larger number of actual device faults than the simple line stuck-at fault model considered at gate level. The proposed approach is based on the encoding of the circuit outputs with Berger codes and by introducing additional networks to provide tolerance to single stuck-on faults and to a relevant number of multiple faults, also reducing to unidirectional faults (and thus detectable with Berger code) the class of not tolerated faults.