A low glitch 14-b 100-MHz D/A converter

A low glitch 14-b 100-MHz current output digital-to-analog converter (DAC) is described. In addition to segmentation of the four most significant bits (MSB's) into 15 equally weighted current sources, a proportional-to-absolute-temperature (PTAT) switching voltage is applied to the current steering devices to minimize glitch over temperature. A bidirectional thin-film trim network and high /spl beta/ n-p-n devices reduce the amount of laser trimming required to achieve 14-b accuracy, resulting in less post-trim degradation of DAC linearity over temperature and the life of the chip. The converter has been fabricated in a 4-GHz/1.4-/spl mu/m BiCMOS technology and exhibits a measured glitch energy of 0.5 pV/spl middot/s (singlet). Settling time to within /spl plusmn/0.012% of the final value is /spl les/20 ns for both rising and falling edges of a full scale step. Spurious free dynamic range (SFDR) for the described converter is 87 dBc at an update rate (f/sub CLK/) of 10 MHz and an output frequency (f/sub OUT/) of 2.03 MHz. The converter operates from +5 V and -5.2 V supplies and consumes 650 mW independent of conversion rate. The chip size is 4.09/spl times/4.09 mm including bond pads and electrostatic discharge (ESD) protection devices.