A memory-efficient continuous-flow FFT processor for Wimax application

This paper presents an area-efficient continuous-flow FFT/IFFT processor for Wimax application. Especially, the integration design of FFT processors with other functional blocks is considered according to Wiamx specification. A new memory scheduling scheme targeted for UL-PUSC transmission mode is proposed to reduce about 50% total memory space requirement compared with the conventional ping-pong based approach. In addition, a cascaded and pipelined PE structure is designed for high speed operation. The structure is configurable to support different FFT size efficiently, especially for those non-power-of-8 DFT operations. The EDA synthesis results show that the proposed FFT processor occupies only 1.62 mm
²
area based on TSMC 0.18-um process.