Automatic generation of Coprocessor program from VHDL description

The design and implementation of complex embedded systems including custom hardware and software is still to a large degree based on a collaboration of semi-manual and often poorly interconnected design methods and tools. This usually results in repetitive and longer development cycles. This paper describes an intelligent method to automate and accelerate the hardware generation process. Indeed, a VHDL parser is developed to provide an automated path from VHDL entry to Coprocessor design. To prove the correctness of our method, a Java source code framework named Automatic Custom Architecture generator (ACAgen) is developed. Experimental results on 3D sample application show that the proposed framework can rapidly and easily generate coprocessor. It leads to the design of large and complex systems-on-chip with less costs and higher performances.