Administration- and communication-aware IP core mapping in scalable multiprocessor system-on-chips via evolutionary computing

In this paper, we address the problem of an efficient mapping of intellectual property (IP) cores onto a multiprocessor system-on-chip (MPSoC). The MPSoC is statically scalable in terms of number of IP cores and an 1-ary n-mesh network-on-chip (NoC). The approach places more affine IP cores closer to each other and affinity is based on an amount of exchanged communication and administration data. Assuming ideal network conditions, accounting for execution latency, separate affinity value matrices for communication and administration are extracted from the application mappings. Aiming at better system performance, the goal is to find a reasonable tradeoff between communication and administration affinity. Hence, both matrices are merged into a single affinity value matrix based on linear weighting. A genetic algorithm (GA) and a mixed-integer linear programming (MILP) solution use the weighted affinity value matrix to efficiently map IP cores onto a NoC. A scalability analysis shows that the GA generates results faster and with a satisfactory quality relative to the found MILP solutions. Realistic benchmark results demonstrate that a tradeoff between administration and communication affinity significantly reduces administration latency improving application performance. As network size and system adaptability increase, the growing influence of administration becomes more evident.