Learning CMOS logic gate design by exploring switch network domain

Switch networks are the basis for digital electronic design regardless the current technology applied. However, such topic has not been deeply explored in CMOS integrated circuits due to particularities and electrical restrictions of CMOS gates, which concentrate in quite simple and basic functions. This paper proposes a new pedagogical way for learning logic gate design starting from switch network building. Next, different CMOS design styles are presented according to the network (logic planes) combinations, i.e., the gate topology. By doing so, such bottom-up acquiring of concepts focuses initially only on the functional behavior of switch arrangements, treating afterwards the gate topology and electrical characteristics associated to each logic family. An innovative CAD environment, called SwitchCraft, has been developed to assist such novel educational methodology.