Model for energy optimization of baseband architectures in wireless communications

Mobile communication needs battery energy. There is always a trade-off between power consumption and bit-error performance. To investigate this, power modeling of the hardware components is necessary. In this paper, a baseband energy model for VLSI design optimization considering both dynamic and static energy consumption for wireless application with short distance is introduced. Due to the trade-off between dynamic and static energy consumption of CMOS gates, a new design rule for energy aware implementation is presented. As an example, the hardware design of an FFT block is analyzed. Over 70% of the energy is saved after the optimization using the presented energy model.