A simulation study of strain induced performance enhancements in InAs nanowire Tunnel-FETs

This work investigates the strain engineering in InAs nanowire Tunnel-FETs. To this purpose we developed a simulator based on the NEGF formalism and employing an 8×8 k·p Hamiltonian. The model accounts for arbitrary crystal orientations and describes the strain implicitly by a modification of the bandstructure. Elastic and inelastic phonon scattering is also accounted for in the self-consistent Born approximation. Our results show that appropriate strain conditions in InAs Tunnel-FETs enable: (a) a remarkable enhancement of the I
_on
with no significant degradation of the subthreshold slope (SS); (b) large improvements in the I
_off
versus I
_on
tradeoff for low I
_off
and V
_DD
values; (c) significant widening of I
_off
and V
_DD
window where Tunnel-FETs can compete with silicon MOSFETs.