8.5 Gbit/s/port synchronous optical packet-switch

A synchronous optical network interconnecting processor effectively reduces network latency and enhances bandwidth. If however, synchronization is not accurate and stable, skew and jitter in received packets may cause transmission errors. Timing margin design must consider the tolerance of the receiver to the skew and jitter. A theoretical analysis shows that the tolerance is /spl plusmn/12% of a bit period. Synchronization by clock distribution is achieved on an 8.5 Gbit/s/port packet-switch testbed utilizing semiconductor optical amplifier gates. An experiment shows that the sensitivity penalty induced by removing the preamble from the packet header and suppressing guard time is less than 0.5 dB.