Modeling of matrix fault current limiter and its verification

One of the viable solutions for handling the fault current levels in power systems is the use of fault current limiters (FCL). Superconducting fault current limiter (SFCL) is widely accepted as the preferable solution for limitation of fault current level. Matrix-type FCLs show almost good performance in practice and therefore it is necessary to work on their theoretical basis and their modeling. Verification of proposed theoretical models can give a basis for extending studies of SFCLs in digital computers. In this paper, at first, theoretical model of Bi2212 SFCL has been introduced, then MFCL concept and the test circuit have been explained and then simulation results have been presented and from its comparison with results of experimental setup, the proposed theoretical model has been verified. It can help researchers to study what is in their mind in digital computers.