A reliable traversal clock delay evaluation including input slew effect with 3D parasitic interconnect RLC extraction

For a large clock net, skew/delay evaluations were carried out using an accurate distributed parasitic network of 3D multilevel interconnect structures. We identified of 3D multilevel interconnect structures. We identified a reliable parasitic distributed RLC extraction method with the bounded local path 3D numerical simulation by using field solver. With the accurate RLC parasitic interconnect network and input driver for traversal clock delay evaluation, we investigated the impacts of variations in input slew, power supply voltage (V/sub cc/), and driver and load gate sizing on clock delay within the slow ramp region of driver gate as well as in the parasitic interconnect network. Input slew was found to be a dominant factor affecting clock delay sensitivity. This suggests that careful sizing of clock drivers, interconnects, and gate loads is required for minimal traversal clock delay. In addition, we used indirect on-chip electron beam probing to confirm that the simulated clock delays were in reasonable agreement with the measured delays.