On-chip timing slack monitoring

PVT monitors are mandatory to use tunable knobs designed to compensate the variability effects. This paper describes a new on-chip monitoring system, allowing failure anticipation in real-time, in looking at the timing slack of a pre-defined set of observable flip-flops. This system is made of special structures situated near the flip-flops, coupled with a specific detection window generator, embedded within the clock-tree. Validation and performances simulated in a 45 nm technology demonstrate a scalable, low power and low area fine-grain system, easily insertable in a standard CAD flow.