Phase-blender-based FIR noise filtering techniques for ΔΣ fractional-N PLL

This paper presents two FIR noise filtering techniques for ΔΣ fractional-N PLL, i.e. FIR-embedded PI and VCDL-based phase prediction. Without use of multiple CPs, PFDs and dividers, FIR-embedded PI realizes FIR noise filtering by averaging the output phases of interpolators. The FIR-embedded PI has been implemented in a 1 GHz ΔΣ fractional-N PLL and achieves the theoretically maximum bandwidth of 0.1׃
ref
. The PLL, fabricated in a 0.13 µm CMOS, shows a reduction of phase noise by 34 dB. The VCDL-based phase prediction scheme also successfully performs the effective FIR filtering even without use of the multiple interpolators and provides a low power solution for FIR noise filtering in the design of ΔΣ fractional-N PLL.