FPGA implementation of a CORDIC-based radix-4 FFT processor for real-time harmonic analyzer

In this paper, the design of a CORDIC algorithm based radix-4 FFT processor is presented which is primarily intended to be used in power harmonic signal processing. The processor is implemented in a Field Programmable Gate Array (FPGA) that is characteristics of high efficiency, low cost, convenient implementation and short development cycle, and its performance is found to be satisfactory. The choice of the CORDIC algorithm for realizing the basic butterfly operation for the FFT which eliminates the need for storing twiddle factors and angles saves a lot of hardware compared to its counterparts employing other techniques. A dual-port memory structure and the corresponding addressing scheme are used to realize the in-place data access. The address generation unit required for fetching data from and writing results into the dual-port memory in proper sequence, is also incorporated within the chip which houses the controller as well. The full design is implemented using ALTERA CycloneII EP2C8Q208C8 series FPGA requiring approximately 3162 configurable logic blocks.