Closed-form expressions for the coupling capacitance computation between through silicon vias and interconnects for 3D ICs

Three dimensional (3D) integration attempts to keep Moore's Law effectively in the years to come. Through-silicon-vias (TSV) processes offer a step towards 3D integration. In this work, the capacitive coupling between TSVs and (horizontal) interconnects is studied. A closed-form formula is derived by studying the physics of the problem. In the analysis, no fitting techniques are utilized. As results show, the range of validity of the proposed formula covers the current and future TSV geometries with the average error falling within 4-6%.