A multi-objective optimization for memory BIST sharing using a genetic algorithm

The memory BIST insertion involves the simultaneous optimization of several conflicting and competing objectives such as test time and power consumption during the test execution procedure. In this paper, a new memory BIST methodology is proposed which optimizes area overhead, test power and test time. It exploits Genetic Algorithms to find a set of Pareto optimal solutions. Since the designer is given a set of trade-off solutions between the three criteria, thus he can choose the most suitable one for his memory testing needs. The proposed algorithm is rigorously tested using several industrial designs.