In-substrate-bitline sense amplifier with array-noise-gating scheme for low-noise 4F2 DRAM array operable at 10-fF cell capacitance

An in-substrate-bitline sense amplifier (SA) with an array-noise-gating (ANG) scheme - for stable sensing operation in a 4F
²
DRAM array with cell capacitance of under 20 fF - is proposed. A circuit simulation assuming 40-nm-class 4F
²
DRAM chip shows that the SA reduces noise by 58% compared to a conventional SA and achieves stable sensing operation even at cell capacitance of 10 fF.