A 78 $\sim$ 102 GHz Front-End Receiver in 90 nm CMOS Technology

In this letter, a 78 ~ 102 GHz front-end receiver designed in 90 nm CMOS technology is presented. It consists of an ultra-wideband low-noise amplifier, a subharmonic mixer, and an IF buffer. This receiver has a peak gain of 11.8 dB at 94 GHz with the noise figure of 13.4 dB. The measured input-referred 1 dB compression point is -14.5 dBm and the total power dissipation is 18.6 mW. The chip size is 680 × 1020 μm
²
.