Efficiency analysis of switched capacitor doubler

Switched capacitors doubler and triplers are used to step-up dc voltage. They are readily integrable which makes them a good choice for numerous applications. Their power conversion efficiency is limited due to switch drops, parasitic capacitances and resistances. However their efficiency is also inherently limited by the circuit topology. This paper provides an upper bound for the power conversion efficiency of a doubler assuming ideal components. This analysis also provides design guidelines, in terms of capacitor size and switching frequency, for meeting efficiency and ripple goals. An alternate circuit topology is examined that does not have this efficiency bound.