Continuous-time optimization of gate timing for synchronous rectification

Synchronous rectifiers, which use a controlled MOSFET in place of a standard p-n or Schottky rectifier, are an important technology for low-voltage power converters. Conventional control techniques for synchronous rectification are often very conservative, however, leaving room for improvement. This paper presents a method for monitoring current flow to adaptively optimize the relative timing of two gate signals for a buck converter with synchronous rectification. Theoretical development is given, along with experimental results for two low-voltage converters.