A hardware/software codesign method for a general purpose reconfigurable co-processor

Shows a hardware/software codesign method for a computer system with a reconfigurable co-processor. The reconfigurable co-processor is constructed from FPGAs, internal cache and a control part, and is connected to the system bus of the computer system. This paper shows the architecture of the reconfigurable co-processor, a hardware/software separation method and a co-operation method via DMA-based memory sharing. We also show co-operation examples and the effectiveness of our approach for the fast execution of user processes.