Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's

As sub-micron design rules are utilized for IC fabrication, wiring is becoming an important issue in the register-transfer synthesis of high-speed application-specific integrated circuits. This paper proposes a new algorithm that incorporates performance-driven placement in module selection phase of the synthesis. The algorithm not only efficiently exploits multiple module implementations in the design library, but also finds the module placement which minimizes wiring delay. Experimental results on a practical size example show that considering both module and wiring issues, the algorithm is able to improve the design performance more than 20%.