CMOS Programmable Gain Distributed Amplifier With 0.5-dB Gain Steps

A new CMOS programmable gain distributed amplifier with 0.5-dB gain steps is fabricated in a 130-nm process. The circuit is designed to demonstrate broadband (>1 decade) programmable gains with excellent matching and high isolation for use in RF integrated-circuit testing. The measured slope of
S
₂₁
loss is approximately 3 dB/decade over frequencies from 0.8 to 9 GHz where input and output return losses are better than roughly 10 dB; the measured input 1-dB compression point and third-order intermodulation intercept point at 2.78 GHz for the maximum 2.5-dB gain is 1 and 12.5 dBm, respectively. The measured noise figure is below 9.5 dB at 9 GHz. The circuit consumes approximately 40 mW total from 3.1-V analog and 1.5-V digital supplies.