Architectural power management for high leakage technologies

We propose a power-performance trade off methodology for microprocessors. An instruction named slowdown for low power (SLOP) is introduced. Functionally, it resembles the conventional NOP but requires power-specific hardware implementation. Depending upon the power reduction requirement, adequate number of SLOP's are automatically inserted in the instruction stream by the power management hardware. While processing a SLOP, additional power control signals are generated for various units; the ALU is powered down, caches are put in drowsy mode, and register file and pipeline registers may be fully or partially clock-gated. Simulation of a five-stage pipelined 32-bit MIPS processor shows that the SLOP method, termed instruction slowdown (ISD), becomes more effective than a conventional clock slowdown (CSD) when leakage is high. For 32nm CMOS technology, ISD can save more than 70% power compared to about 40% by CSD. The paper shows that power reduction through a judicious choice of slowdown factor and the method adopted, clock slowdown for low leakage and instruction slowdown for high leakage, can enhance the battery lifetime as well.