A Noise Filtering Technique for Fractional-$N$ Frequency Synthesizers

A noise filtering technique for fractional-N frequency synthesizers (FNFSs) is presented. The noise filter is based on an integer-N (N = 1) phase-locked loop that is placed in a feedback path of an FNFS. By adopting the noise filter, out-of-band quantization noise of a high-order delta-sigma modulator is suppressed. In addition, folded noise due to nonlinearity of a phase/frequency detector (PFD) and a charge pump is improved by reducing phase errors at PFDs. An FNFS using the noise filter is fabricated in 90-nm complementary metal-oxide-semiconductor technology. Its die area is 950 by 950 μm, and its power consumption is 30 mW for a supply voltage of 1 V. The frequency resolution of this FNFS is less than 1 Hz.