A 15 ns 2500 gate highly flexible CHMOS EPLD

A 2500-gate, 15-ns CMOS electrically programmable logic device (EPLD) with configurable inputs, expandable sum of products (SOP), and SOP implementation of control signals has been developed. Independent synchronous or asynchronous clocking of the inputs and outputs, plus both internal and pad feedback of each macrocell, makes this an extremely configurable 40-pin logic device. A combination of high speed, high density, and flexible architecture makes this device an ideal solution for high-speed microcomputer system design