A 400 MHz 0.934ps rms jitter multiplying delay lock loop in 90-nm CMOS process

A multiplying delay-locked loop (MDLL) is adopted for low-jitter clock generation. This architecture overcomes the drawback of phase-locked loops (PLL) such as jitter accumulation, and maintain the advantage of a PLL for multirate frequency multiplication. The MDLL, implemented in 90-nm CMOS technology, occupies about 1mm
²
and works at 400MHz with multiplication ratio of 4. The complete synthesizer, including the output buffers, dissipates 31mW from a 1.2V supply at 400MHz. The rms jitter is 0.934ps according to the phase noise integrated from 1KHz to 1MHz, when the output frequency is 400MHz.