Optimization of media processor performance through sub word virtual register design

Subword data is widely used in embedded applications, particularly related to media and network processing. The highest concentration of subword data length in embedded systems is in the 16-bit range. Since the conventional word size is 32-bit, on the average half of the registers remain unoccupied during the register allocation phase. Subword parallelism though less effective as compared to ILP (Instruction Level Parallelism), plays a defining role in latency reduction efforts. The latency issues are important to streaming media processing. In order to provide for the efficient use of registers, new primitive data types are proposed which enables packing of multiple subwords on a register. Since these new data types are operated on conventional instructions, there is very little increase in code size of a program. The work around creates a flexible packing algorithm which prevents the register to remain partially vacant. The use of gate logic to solve the subword packing in registers makes the algorithm efficient and fast. The technique further creates an opportunity to have a single programmable core for different application-specific media needs. In addition to this the use of simplified gate logic for the algorithm implementation makes the hardware implementation/mapping of the algorithm much easier and error free.