A 2-path /spl Sigma//spl Delta/ modulator for bandpass applications

This article presents a low-power bandpass sigma-delta modulator using a multibit quantizer (9 levels) and switched-capacitor DAC. The circuit is being manufactured in the 0.5 /spl mu/m CMOS technology to operate with a 3.3-/spl nu/ power supply. The sampling frequency Fs=24.576 MHz has been chosen to be equal to 4 times the intermediate frequency fo=6.144 MHz. Computer simulations revealed a SNR=60 dB (10 bits) with a bandwith of 1.536 MHz, that is to say OSR=8. The power consumption is evaluated at 25 mW and the integration surface at about 2 mm/sup 2/. The performance evaluation is based on the test results of a previous circuit designed on the same basis (a 1-bit 4th-order bandpass /spl Sigma//spl Delta/ modulator).