Offset current cancellation based on a multiple-path feedback compensation (MPFC) technique for switched-current circuits and systems

This paper presents a new offset current cancellation technique called multiple-path feedback compensation (MPFC) for greatly reducing offset currents at both output and internal nodes of SI circuits and systems. In order to analyze the effects and the statistical distribution of DC current offsets of large SI systems, a very simple and efficient SI model is first used. This model can be used for fast, accurate, statistical, and systematic analyzes of system characteristics such as offset current, frequency response, stability, scaling, and sensitivity. Based on the model, a complex SI system can be transferred to a simple signal flow graph, which can be represented by linear state equations. From the state equations, statistical Monte Carlo simulation is used to obtain optimal MPFC coefficients. A fifth-order Chebyshev SI filter is illustrated as an example for implementation and verification of the proposed MPFC technique. Ninety test chips have been fabricated with a 1-/spl mu/m CMOS n-well digital process. Increased percentages of circuit area and power consumption due to the use of the MPFC circuit are 5% and 4%, respectively. Measured results show that the variance of output offset currents is reduced to 2% of its original amount. Besides, the peak signal-to-noise ratio (PSNR) is increased by 3 dB and the total harmonic distortion is reduced by 10 dB.