Scalable Fualt Detection for FPGAs

Field Programmable Gate Arrays (FPGA) offer many advantages to the designers of systems including high predictability in terms of resource usage and the ability to process certain (parallel) functions and data streams efficiently and quickly. To date an impediment against the use of FPGA in safety critical domains is a lack of appropriate fault tolerance techniques. This has resulted in them being used mainly in lower criticality systems often with rudimentary and inefficient fault tolerance schemes, e.g. triple-modular redundancy. Our previous work has developed a Failure Propagation Transformation Calculation (FPTC) to help analyse how Single Effect Upsets (SEU) can lead to hazards. However, there are issues with this approach to do with scalability and identifying the source of any fault. In this paper we address the issue of fault diagnosis through concept of alarm placement.