The design of an ASIC-multiplexer used in digital communication

This paper presents a novel design of communication ASIC multiplexer, which is an asynchronous system with positive code speed justification and consists of about eighty thousand integrated MOSFETs. In the multiplexer, the clocking block and digital locked-loops were designed. The designed system can be used in two different modes: the system allows 2/8 Mb multiplexing function of 8/34 Mb multiplexing function. This design was simulated and verified by EDA tool CADENCE Software, and the multiplexing function had been accomplished by FPGA.