A methodology for high level synthesis of high performance DSP structures targetting FPGAs

High level synthesis transforms a given behavioral specification into a register transfer level that can implement the given behavior. In this paper a novel technique that combines heuristics and mathematical programming formulation of the synthesis problem is introduced. This technique exploits features of the implementation hardware FPGAs and explore larger solution space than previous approaches. In this paper we particularly emphasize the importance of the optimization function that should be multi faceted. We simultaneously optimize the performance of the architecture, while minimizing the area and interconnections used in a given chip. The effect of deep pipe-lining and multi level chaining is demonstrated. The efficiency of our approach is demonstrated by comparing the results for typical high level synthesis benchmarks.