Pin allocation for clock routing

We present two algorithms for allocating clock pin positions to reduce connection, length while maintaining zero clock skew. For the channel routing case, a graph model is introduced to precisely represent the problem. Based on the model, a clock tree with minimal length, depth and skew is obtained. For a given placement, the depth of the clock tree is proved to be minimal while minimizing the clock net length, therefore the latency of the clock net can be predicted accurately. For the case of BBL design methodology the connection lengths are reduced by setting the pitch-matching point among the adjacent modules. This significantly increases the local connectivity and decreases the global connectivity of the clock net. Comparatively good results over those published were achieved. Up to 35% improvements on net lengths were made in the BBL cases.