Fast and flexible pipelined multi-processor architecture for multimedia device

This paper proposes a fast and efficient multi-processor architecture for devices a requiring high speed performance. The proposed method connects four basic processor modules (BPM) including CPU's in a pipeline shape to enhance execution speed. Also, using a specific BPM selectively regarding to multimedia applications increases the efficiency, and has more flexibility by software implementation for needed functions without hardware replacement than using a hardware accelerator. This has been implemented using Verilog HDL and its performance is compared and analyzed in terms of complexity and speed of execution. Even the complexity of the proposed architecture increases 20% compared with the multi-core CPU method, speed increases 52%.