Cycle time reduction program at ACL

In this paper we focus on the results of the DRAM production cycle time team with special emphasis on: how does CT translate into productivity; what tools are needed for effective CT analysis including daily going rate (DGR) issues; how to find and how to fight the main CT detractors The results are compared with the real world execution at the SIEMENS/IBM Advanced CMOS line (ACL) in Essonnes-Corbeil.