Fault tolerant systolic evaluation of polynomials and exponentials of polynomials for equispaced arguments

Many applications in digital signal processing and computer graphics, which require high speed evaluation of polynomials and exponentials of polynomials can now be implemented in hardware very efficiently because of the advances in VLSI technology. Several fast algorithms have been proposed in the recent past for the efficient evaluation of polynomials and exponentials of polynomials for equispaced arguments on uniprocessor systems. In this brief, we consider the problem of organizing this evaluation on VLSI chips in the form of systolic arrays. We use triple time redundancy and algorithm-based fault tolerance to detect and correct errors caused by transient failures in the Processing Elements (PEs) of these systolic arrays. A comparison of the space and time overheads in using these two methods for adding fault tolerance is also discussed.