A Phase-Locked Loop With Background Leakage Current Compensation

A background compensation method is presented to compensate the leakage current of MOS capacitors for phase-locked loops (PLLs) in nanoscale CMOS technology. A leakage detection circuit is used to adjust a voltage-controlled current source to compensate the leakage current. This PLL has been fabricated in 65-nm CMOS technology. With the background leakage current compensation, the measured peak-to-peak and rms jitters of this PLL at 1 GHz are 36 and 4.54 ps, respectively. Its power consumption is 8.4 mW for a 1.2-V supply voltage.