Analysis and implementation of Raptor codes on embedded systems

Raptor codes have been proven very suitable for mobile multimedia content delivery, and yet they have not been analyzed in the context of embedded systems. At the heart of Raptor codes for binary erasure channel (BEC) is the matrix inversion operation. This paper analyzes the performance, energy profile and resource implication of two matrix inversion algorithms for the Raptor decoder on a system on a chip (SoC) platform with a soft-core embedded processor. We show how the cache size, matrix memory type and organization affect the two algorithms under consideration.