Pixel cache architecture with FIFO implemented within an ASIC

Implementation technology for 3D pixel cache and performance evaluation of a graphics processor Truga001, with 12 embedded processors within a single chip, are described. The chip can render 4 million vectors/s (10 pixels/vector) or 1.2 million triangle polygons/s (100 pixels/polygon) with Phong shading, texture mapping and hidden surface removal. A pixel-array configured with 8(x)/spl times/4(y)/spl times/24-bit(intensity)/spl times/24-bit(z) can be accessed with frame buffer at 180 ns due to the 3D bus-architecture between chip and frame buffer. The chip was designed with Toshiba TC180C CMOS of 400,000 gates.