A calibration-free 800MHz fractional-N digital PLL with embedded TDC

An 800 MHz digital PLL with its TDC embedded within the DVCO is implemented in 65 nm CMOS and occupies 0.027 mm
²
. The design requires no calibration and achieves the fractional-N operation without a multi-modulus feedback divider. To further improve the TDC linearity, mismatch filtering is used to achieve a DNL of less than 3.5% of LSB.