Transition reduction in carry-save adder trees

By taking advantage of the redundancy in a 4-2 compressor, we reduce the number of transitions in carry-save adder trees that are common in large multipliers. Three new 4-2 compressors are proposed. These are used in different configurations to reduce the probability of a transition in the global carry wires by up to 40% over current techniques. Power reductions are demonstrated with the use of a 4-tap FIR filter module and a 54/spl times/54-bit multiplier. Transistor level circuit simulations indicate 5-6% power reduction with no increase in delay.