Buffer size trade-offs in input/output buffered ATM switches under various conditions

In this paper the non-linear and complex relationship between packet loss probability and average packet delay for an input/output buffered ATM switch is studied thoroughly using our previously published analysis model. The main contribution is insight into the behavior of the switch and better understanding of the buffer size trade-offs under various traffic conditions speed-up factors, and buffer sizes. For different traffic conditions and buffer sizes, several distinct regions are identified and the behavior of the switch in those regions is explained. The results presented here can provide the basis for an optimum VLSI design methodology for input/output-buffered switches.