Design and Fabrication of Subnanosecond Current Switch and Transistors

A junction-isolated integrated circuit in silicon is described, having a switching speed of 320 picoseconds in a package which by itself causes a 120 ps delay. The design of the transistor used in this circuit was obtained by simulating the transistor as a computerized, two-dimensional distributed model. The improvements required in the transistor technology were thus predetermined and the design was realized without a large number of iterations. It is shown that the primary parameters affecting the performance of the transistor are (a) mobile carrier storage in the emitter-base junction; (b) emitter crowding; (c) stretching of the base into the collector at high forward-current densities and (d) conductivity modulations in the active base region. The resulting transistors have a cut-off frequency of 7.15 GHz at V
CB
=2 V and I
C
=20 mA. The total number of impurity atoms forming the emitter and the base region are 5.57×10
⁹
and 5.7×10
⁵
, respectively.