Asymmetry and mismatch in CMOSFETs with source/drain regions fabricated by various ion-implantation methods

Experimental results on asymmetry and mismatch (A&M) characteristics are discussed for 0.5 /spl mu/m surface-channel n-MOSFETs and buried-channel p-MOSFETs fabricated by four ion-implantation methods and designed by a conventional and a side-by-side layout. The side-by-side layout is useful to improve A&M caused by source/drain asymmetry. There is not a single choice that simultaneously satisfies the minimum average and deviation values of A&M for all electrical parameters. For minimizing A&M in (I/sub D/ and /spl beta/), (V/sub T/ and S) and I/sub B/, n- and p-MOSFETs fabricated by 7/spl deg//spl times/4-implantation, n-MOSFETs with 0/spl deg/- and 7/spl deg//spl times/4-implantation, and n- and p-MOSFETs with 0/spl deg/- and 7/spl deg//spl times/4-implantation are recommended, respectively. However 0/spl deg/-implanted MOSFETs must not be used because of their inferior punchthrough characteristics.