A LUT-based VRC model for random logic function evolution

Recently, the VRC (Virtual Reconfigurable Circuit) has become a mainstream solution for EHW (Evolvable Hardware) research. In this paper, A LUT-based VRC model is proposed, which can be applied for random logic function evolution. Different kinds of LUTs with appropriate interconnections were studied on a FPGA-based platform. Research were also performed in this platform to compare with the current VRC model such as VRC1 [SinMan] and VRC2 [Sekan-ina]. The results show that 3-input LUT with a direct interconnection achieves about 8% improvement in fitness value after 20,000 generations, and obtains obvious progress in logic resource utilization rate.