Full wave analysis of transmission lines in a multilayer substrate with heavy dielectric losses

The worldwide CMOS integrated circuits industry relies on heavily doped silicon wafers as the starting material for chip fabrication; the resulting integrated circuits are confined to the upper few microns of the wafer, which itself is as much as 600-/spl mu/m thick. These heavily doped silicon substrates are not insulators, but are actually very lossy; a loss tangent of 10/sup 5/ at 1 MHz is a fairly typical characteristic of the wafers. Although it is becoming increasingly necessary to model accurately the currents which flow between transistors and interconnects into the substrates, existing computer-aided design (CAD) simulation packages fail to provide accurate results in modeling such heavy dielectric losses, because most CAD packages rely on small perturbation methods in the analysis of dielectric losses. In this paper, the problem of computing the electrical behavior of lossy dielectrics is analyzed by the full wave method, and the mutual capacitances of transmission lines above such heavily doped CMOS substrates are computed and compared with laboratory experimental measurements. Good agreement between analytical and measurement results has been obtained.